TC1115 Datasheet, PDF (31/103 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller Advance Information

TC1115
Advance Information
Functional Description
3.3
Memory Protection System
The TC1115 memory protection system specifies the addressable range and read/write
permissions of memory segments available to the currently executing task. The memory
protection system controls the position and range of addressable segments in memory.
It also controls the types of read and write operations allowed within addressable
memory segments. Any illegal memory access is detected by the memory protection
hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the
error. Thus, the memory protection system protects critical system functions against both
software and hardware errors. The memory protection hardware can also generate
signals to the Debug Unit to facilitate tracing illegal memory accesses.
In TC1115, TriCore™ supports two address spaces: the virtual address space and the
physical address space. Both address space are 4 Gbytes in size and divided into
16 segments with each segment being 256 Mbytes. The upper 4 bits of the 32-bit
address are used to identify the segment. Virtual segments are numbered 0 - 15. But a
virtual address is always translated into a physical address before accessing memory.
The virtual address is translated into a physical address using one of two translation
mechanisms: (a) direct translation, and (b) Page Table Entry (PTE) based translation. If
the virtual address belongs to the upper half of the virtual address space then the virtual
address is directly used as the physical address (direct translation). If the virtual address
belongs to the lower half of the address space, then the virtual address is used directly
as the physical address if the processor is operating in physical mode (direct translation)
or translated using a Page Table Entry if the processor is operating in virtual mode (PTE
translation). These are managed by Memory Management Unit (MMU).
Memory protection is enforced using separate mechanisms for the two translation paths.
3.3.1 Protection for Direct translation
Memory protection for addresses that undergo direct translation is enforced using the
range based protection that has been used in the previous generation of the TriCore™
architecture. The range based protection mechanism provides support for protecting
memory ranges from unauthorized read, write, or instruction fetch accesses. The
TriCore™ architecture provides up to four protection register sets with the PSW.PRS
field controlling the selection of the protection register set. Because the TC1115 uses a
Harvard-style memory architecture, each Memory Protection Register Set is broken
down into a Data Protection Register Set and a Code Protection Register Set. Each Data
Protection Register Set can specify up to four address ranges to receive particular
protection modes. Each Code Protection Register Set can specify up to two address
ranges to receive particular protection modes.
Each of the Data Protection Register Sets and Code Protection Register Sets
determines the range and protection modes for a separate memory area. Each contains
register pairs which determine the address range (the Data Segment Protection
Registers and Code Segment Protection Registers) and one register (Data Protection
Data Sheet
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V1.0, 2005-02