TC1115 Datasheet, PDF (39/103 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller Advance Information

TC1115
Advance Information
Functional Description
3.7
Interrupt System
An interrupt request can be serviced by the CPU, which is called “Service Provider”.
Interrupt requests are referred to as “Service Requests” in this document.
Each peripheral in the TC1115 can generate service requests. Additionally, the Bus
Control Unit, the Debug Unit, the DMA Controller and even the CPU itself can generate
service requests to the Service Provider. As shown in Figure 3-3, each unit that can
generate service requests is connected to one or multiple Service Request Nodes
(SRN). Each SRN contains a Service Request Control Register mod_SRC, where “mod”
is the identifier of the unit requesting service. The SRNs are connected to the Interrupt
Control Unit (ICU) via the CPU Interrupt Arbitration Bus. The ICU arbitrates service
requests for the CPU and administers the Interrupt Arbitration Bus.
Units that can generate service requests are:
• Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1 and ASC2) with 4 SRNs
each
• High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) with 3 SRNs each
• Inter IC Interface (IIC) with 3 SRNs
• Micro Link Interface MLI0 with 4 SRNs and MLI1 with 2 SRNs
• General Purpose Timer Unit (GPTU) with 8 SRNs
• Capture/Compare Unit (CCU60 and CCU61) with 4 SRNs each
• MultiCAN (CAN) with 16 SRNs
• External Interrupts with 4 SRNs
• Direct Memory Access Controller (DMA) with 4 SRNs
• DMA Bus with 1 SRN
• System Timer (STM) with 2 SRNs
• Bus Control Units (SBCU and LBCU) with 1 SRN each
• Central Processing Unit (CPU) with 4 SRNs
• Floating Point Unit (FPU) with 1 SRN
• Debug Unit (OCDS) with 1 SRN
The CPU can make service requests directly to itself (via the ICU). The CPU Service
Request Nodes are activated through software.
Data Sheet
33
V1.0, 2005-02