TC1115 Datasheet, PDF (19/103 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller Advance Information

TC1115
Advance Information
General Device Information
Table 2-1 Pin Definitions and Functions (cont’d)
Symbol Pin
HDRST N5
PORST R5
NMI
T7
TRST
T11
TCK
T12
TDI
T13
TDO
T10
TMS
T9
TRCLK T8
HWCFG0 M14
HWCFG1 L14
HWCFG2 T6
BRKIN T5
In PU/ Functions
Out PD¹⁾
I/O PUA Hardware Reset Input/Reset Indication Output
Assertion of this bi-directional open-drain pin causes a
synchronous reset of the chip through external
circuitry. This pin must be driven for a minimum 4 f_CPU
clock cycles.
The internal reset circuitry drives this pin in response
to a power-on, hardware, watchdog and power-down
wake-up reset for a specific period of time. For a
software reset, activation of this pin is programmable.
I PUC Power-on Reset Input
A low level on PORST causes an asynchronous reset
of the entire chip. PORST is a fully asynchronous level
sensitive signal.
I PUC Non-Maskable Interrupt Input
A high-to-low transition on this pin causes an
NMI-Trap request to the CPU.
I PDC JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG
module. A high level enables the JTAG module.
I PUC JTAG Module Clock Input
I PUC JTAG Module Serial Data Input
O  JTAG Module Serial Data Output
I PUC JTAG Module State Machine Control Input
O  Trace Clock for OCDS_L2 Lines
I PUC Hardware Configuration Inputs
I PUC The Configuration Inputs define the boot options of the
I PDC TC1115 after a hardware invoked reset operation.
I PUC OCDS Break Input
A low level on this pin causes a break in the chip’s
execution when the OCDS is enabled. In addition, the
level of this pin during power-on reset determines the
boot configuration.
Data Sheet
13
V1.0, 2005-02