TC1115 Datasheet, PDF (32/103 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller Advance Information

TC1115
Advance Information
Functional Description
Mode Register) which determines the memory access modes which apply to the
specified range.
3.3.2 Protection for PTE based translation
Memory protection for addresses that undergo PTE based translation is enforced using
the PTE used for the address translation. The PTE provides support for protecting a
process from unauthorized read, write, or instruction fetches by other processes. The
PTE has the following bits that are provided for the purpose of protection:
• Execute Enable (XE) enables instruction fetch to the page
• Write Enable (WE) enables data writes to the page
• Read Enable (RE) enables data reads from the page
Furthermore, User-0 accesses to virtual addresses in the upper half of the virtual
address space are disallowed when operating in virtual mode. In physical mode, User-0
accesses are disallowed only to segments 14 and 15. Any User-0 access to a virtual
address that is restricted to User-1 or supervisor mode will cause a Virtual Address
Protection (VAP) Trap in both the physical and virtual modes.
3.3.3 Memory Checker
The Memory Checker module (MCHK) makes it possible to check the data consistency
of memories. It uses DMA moves to read from the selected address area and to write the
value read in a memory checker input register (the moves should be 32-bit moves). A
polynomial checksum calculation is done with each write operation to the memory
checker input register.
Data Sheet
26
V1.0, 2005-02