TC1115 Datasheet, PDF (37/103 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller Advance Information

TC1115
Advance Information
Functional Description
3.6
Direct Memory Access (DMA)
The Direct Memory Access Controller executes DMA transactions from a source
address location to a destination address location, without intervention of the CPU. One
DMA transaction is controlled by one DMA channel. Each DMA channel has assigned
its own channel register set. The total of 8 channels are provided by one DMA sub-block.
The DMA module is connected to 3 bus interfaces in TC1115, the Flexible Peripheral
Interconnect Bus (FPI), the DMA Bus and the Micro Link Bus. It can do transfers on each
of the buses as well as between the buses.
In addition, it bridges accesses from the Flexible Peripheral Interconnect Bus to the
peripherals on the DMA Bus, allowing easy access to these peripherals by CPU. Clock
control, address decoding, DMA request wiring, and DMA interrupt service request
control are implementation specific and managed outside the DMA controller kernel.
Features:
• 8 independent DMA channels
– Up to 8 selectable request inputs per DMA channel
– Programmable priority of DMA channels within a DMA sub-block (2 levels)
– Software and hardware DMA request generation
– Hardware requests by selected peripherals and external inputs
• Programmable priority of the DMA sub-block on the bus interfaces
• Buffer capability for move actions on the buses (min. 1 move per bus is buffered).
• Individually programmable operation modes for each DMA channel
– Single mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated.
– Programmable address modification
• Full 32-bit addressing capability of each DMA channel
– 4-Gbyte address range
– Support of circular buffer addressing mode
• Programmable data width of a DMA transaction: 8-bit, 16-bit, or 32-bit
• Micro Link supported
• Register set for each DMA channel
– Source and destination address register
– Channel control and status register
– Transfer count register
• Flexible interrupt generation (the service request node logic for the MLI channels is
also implemented in the DMA module)
• All buses/interfaces connected to the DMA module must work at the same frequency.
• Read/write requests of the FPI Bus Side to the Remote Peripherals are bridged to the
DMA Bus (only the DMA is master on the DMA bus)
Data Sheet
31
V1.0, 2005-02