TC1115 Datasheet, PDF (58/103 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller Advance Information

TC1115
Advance Information
Functional Description
3.16
System Timer
The STM within the TC1115 is designed for global system timing applications requiring
both high precision and long range. The STM provides the following features:
• Free-running 56-bit counter
• All 56 bits can be read synchronously
• Different 32-bit portions of the 56-bit counter can be read synchronously
• Flexible interrupt generation on partial STM content compare match
• Driven by clock f_STM after reset (default after reset is f_STM = f_SYS = 150 MHz)
• Counting starts automatically after a reset operation
• STM is reset under following reset causes:
– Wake-up reset (PMG_CON.DSRW must be set)
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
• STM (and the clock divider) is not reset at watchdog reset and hardware reset
(HDRST = 0)
The STM is an upward counter, running with the system clock frequency f_SYS (after reset
f_STM = f_SYS). It is enabled per default after reset, and immediately starts counting up.
Other than via reset, it is not possible to affect the contents of the timer during normal
operation of the application; it can only be read, but not written to. Depending on the
implementation of the clock control of the STM, the timer can optionally be disabled or
suspended for power-saving and debugging purposes via a clock control register.
The maximum clock period is 2⁵⁶/f_STM. At f_STM = 150 MHz (maximum), for example, the
STM counts 15.2 years before overflowing. Thus, it is capable of continuously timing the
entire expected product lifetime of a system without overflowing.
Data Sheet
52
V1.0, 2005-02