TC1728 Datasheet, PDF (8/130 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1728
Summary of Features
– 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
• High performing on-chip bus structure
– 64-bit Local Memory Buses between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (LFI Bridge)
• Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– One serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
– One High-Speed Micro Link interface (MLI) for serial inter-processor
communication
– One MultiCAN Module with 3 CAN nodes and 64 free assignable message objects
for high efficiency data handling via FIFO buffering and gateway data transfer
– One FlexRay^TM module with 2 channels (E-Ray).
– One General Purpose Timer Array Module (GPTA) providing a powerful set of
digital signal filtering and timer functionality to realize autonomous and complex
Input/Output management
– Two Capture/Compare Unit 6 (CAPCOM6) kernels
– Two General Purpose Timer (GPT12) modules
• 36 analog input lines for ADC
– 2 independent kernels (ADC0 and ADC1)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
– Broken wire detection
• 2 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of f_FADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
• 127 digital general purpose I/O lines (GPIO), 3 input lines
• Digital I/O ports with 3.3 V capability
• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)
• Dedicated Emulation Device chip available (TC1728ED)
– multi-core debugging, real time tracing, and calibration
– four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
• Power Management System
• Clock Generation Unit with PLL
Data Sheet
1-3
V1.2, 2014-06