TC1728 Datasheet, PDF (109/130 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1728
Electrical Parameters
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
The MLI parameters are valid for C_L = 50 pF, strong driver medium edge.
Table 34 MLI Receiver
Parameter
Symbol
Min.
Values
Unit Note /
Typ. Max.
Test Condition
RCLK clock period
t₂₀ SR 1 / f_FPI −
−
ns
RCLK high time¹⁾²⁾
t₂₁ SR −
0.5 x t₂₀ −
ns
RCLK low time¹⁾²⁾
t₂₂ SR −
0.5 x t₂₀ −
ns
RCLK rise time³⁾
t₂₃ SR −
−
4
ns
RCLK fall time³⁾
t₂₄ SR −
−
4
ns
RDATA/RVALID setup t₂₅ SR 4.2
−
time before RCLK falling
−
ns
edge
RDATA/RVALID hold t₂₆ SR 2.2
−
time after RCLK falling
edge
−
ns
RREADY output delay t₂₇ SR 0
−
16
ns
time
1) The following formula is valid: t21 + t22 = t20.
2) Min and Max values for this parameter can be derived from the typ. value by considering the other receiver
timing parameters.
3) The RCLK max. input rise/fall times are best case parameters for fFPImax. For reduction of EMI, slower input
signal rise/fall times can be used for longer RCLK clock periods.
Table 35 MLI Transmitter
Parameter
Symbol
Values
Min. Typ. Max.
TCLK clock period
TCLK high time¹⁾²⁾
TCLK low time¹⁾²⁾
t₁₀ CC
t₁₁ CC
t₁₂ CC
2x1/
f_FPI
0.45 x
t₁₀
0.45 x
t₁₀
−
0.5 x
t₁₀
0.5 x
t₁₀
−
0.55 x t₁₀
0.55 x t₁₀
Unit Note /
Test Condition
ns
ns
ns
Data Sheet
5-63
V1.2, 2014-06