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TC1728 Datasheet, PDF (75/130 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller
TC1728
Electrical Parameters
Table 22 3.3V ADC Parameters
Parameter
Symbo
Values
Unit
l
Min. Typ. Max.
Note /
Test Condition
Resistance of the
reference voltage input
path
RAREF −
CC
Broken wire detection
delay against VAGND
Broken wire detection
delay against VAREF
tBWG
−
CC
tBWR CC −
1700 3000
− 50
Ohm
13)
500 Ohm
increased if
AIN[1:0] used
as reference
input
− 50
14)
Sample time
tS CC 2
−
257
TADCI
Calibration time after bit tCAL CC −
ADC_GLOBCFG.SUCAL
is set
− 4352 cycles
Total Unadjusted
Error5)6)15)
TUE -4.5
−
4.516) LSB ADC
CC
resolution= 12-
bit
Analog reference
ground2)
VAGND0 VSSM - −
SR 0.05
Analog input voltage
VAIN SR VAGND0 −
Analog reference
voltage2)
VAREF0
SR
VAGND0 −
+
VDDM/2
Analog reference voltage VAREF0 - VDDM/2 −
range5)6)2)
VAGND0
SR
VAREF0 V
-
VDDM/2
VAREF0 V
VDDM + V
0.0517)
18)
VDDM + V
0.05
1) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements the voltage measured at AINx can deviate from VAREF/2.
2) Applies to AINx, when used as auxiliary reference input.
3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead smaller capacitances are successively switched to the reference voltage.
4) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
5) If the analog reference voltage range is below VDDM but still in the defined range of VDDM / 2 and VDDM is used,
then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1),
TUE,DNL,INL,Gain, and Offset errors increase also by the factor 1/k.
Data Sheet
5-29
V1.2, 2014-06