TC1728 Datasheet, PDF (113/130 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1728
5.3.11.3 SSC Master/Slave Mode Timing
Electrical Parameters
The SSC parameters are valid for C_L = 50 pF, strong driver medium edge.
Table 37
Parameter
Parameters
Symbol
Min.
Values
Typ. Max.
SCLK clock period¹⁾²⁾³⁾
t₅₀ CC
2x1/ −
−
f_FPI
MTSR/SLSOx delay from t₅₁ CC
0
−
8
SCLK rising edge
MRST setup to SCLK
t₅₂ SR
16.5 −
−
latching edge³⁾
MRST hold from SCLK t₅₃ SR
0
−
−
latching edge³⁾
SCLK input clock
period¹⁾³⁾
t₅₄ SR
4x1/ −
−
f_FPI
SCLK input clock duty
t₅₅_t₅₄ SR 45
−
55
cycle
MTSR setup to SCLK
t₅₆ SR
1 / f_FPI −
−
latching edge³⁾⁴⁾
+1
MTSR hold from SCLK t₅₇ SR
1 / f_FPI −
−
latching edge
+5
SLSI setup to first SCLK t₅₈ SR
1 / f_FPI −
−
latching edge
+5
SLSI hold from last SCLK t₅₉ SR
7
−
−
latching edge⁵⁾
MRST delay from SCLK t₆₀ CC
0
−
16.5
shift edge
SLSI to valid data on
t₆₁ CC
−
−
16.5
MRST
1) SCLK signal rise/fall times are the same as the rise/fall times of the pad.
2) SCLK signal high and low times can be minimum 1xT.
3) Tmin = TSYS = 1/fSYS.
4) Fractional divider switched off, internal baud rate generation used.
Unit Note /
Test Conditi
on
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
Data Sheet
5-67
V1.2, 2014-06