TC1728 Datasheet, PDF (127/130 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1728
Revision History
• Removed capacitance conditions for LVDS pad parameters, t_RL, t_FL , loads defined by
interface (MSC) timing.
• Updated max limits of Flash parameters t_PRD, t_PRP
• Updated representation of I_DDP
• Updated limits of I_{DD_PORST} to max 110mA
• Updated limits of I_{DDP_PORST} to max 6mA
• Updated limits of I_DD for real pattern, f_CPU=133MHz, to max 212mA
• Added new parameter I_DDSUM
• Updated max limit of I_DDM to 32mA
• Updated TC1728 I_V5 for max and real patterns, f_CPU=133MHz
• Updated PD for real pattern, f_{CPU=133MHz, all external supplies.}
• Updated TC1728 PD for max and real patterns, f_{CPU=133MHz, 5V only with external pass device.}
• Updated limit for R_DSON2 of A2 pad, P_MOS
• Updated limits for R_DSONM of F pad, P_MOS, N_MOS
• Removed V_IH for Pass Device Detector
• Updated limits for V_IL of Pass Device Detector
• Updated limits and test conditions for ∆V_LOREG33 and ∆V_LIREG33
• Updated test condition for 5.0V single supply ∆V_LOREG13
• Updated limits and test condition for 5.0V single supply ∆V_LIREG13
• Corrected typ and max limits for C_OUT33 and C_OUT13
• Added limit and test condition for 3.3V single supply ∆V_LOREG13 and ∆V_LIREG13
• Application reset boot time limits are updated
• Added min limit for I_OZS
• Added a new parameter V_ILSD
• Updated limits for t_BP, STT
• Removed typical text from load of Peripheral Timing sections.
• Limits for EF_GRAD with Gain=4 is changed to TBD
• Min limit for V_DDM is changed to TBD
• Added EF_REFI
• Added a placeholder for R_FAIN, EF_DNL, EF_INL, EF_GRAD, EF_OFF at a separate ADC table
for V_DDM=3.3V
• Added max and typ limits for R_RAIN for V_DDM=3.3V
• Updated limits of P_D for real pattern, f_CPU=80MHz, to max 669mW
• Updated text for Note column of N_E
• Corrected typo for Class D pads in PN-Junction Characteristics for positive/negative
overload tables
• Updated limits of I_DD for max pattern, f_CPU=133MHz, to max 310mA
• Updated limits of I_DD for max pattern, f_CPU=80MHz, to max 248mA
• Updated limits of P_D for max pattern, f_CPU=133MHz, to max 902mA
• Updated limits of I_DD for max pattern, f_CPU=80MHz, to max 810mA
• Corrected typo for C_OUT13
• Updated load jump current for C_OUT33 and C_OUT13 for f_CPU=80MHz
• Changed min to typ value for C_IN5
Data Sheet
6-5
V1.2, 2014-06