HYB39L256160AC Datasheet, PDF (8/48 Pages) Infineon Technologies AG – 256 MBit Synchronous Low-Power DRAM

HYB 39L256160AC / T
256MBit 3.3V Mobile-RAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and xDQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Bank Active
Device
State
Idle³
Bank Precharge
Any
Precharge All
Write
Any
Active³
Write with Autoprecharge Active³
Read
Active³
Read with Autoprecharge Active³
Mode Register Set⁴
Idle
No Operation
Any
Burst Stop
Active
Device Deselect
Any
Auto Refresh
Idle
Self Refresh Entry
Idle
Self Refresh Exit
Self
Refresh
Clock Suspend Entry
Active⁵
Clock Suspend Exit
Active
Power Down Entry
(Precharge standby or
active standby)
Idle
Active⁵
Power Down Exit
Any
Power
Down
Data Write/Output Enable Active
Data Write/Output
Disable
Active
CKEn-1 CKEn DQM BA0 AP= Addr CS RAS CAS WE
BA1 A10
H
X
X
VV
VLL
HH
H
X
X
V
L
XLL
HL
H
X
X
X H XLL
HL
H
X
X
V
L
VLH
LL
H
X
X
V H VLH
LL
H
X
X
V
L
VLH
LH
H
X
X
V H VLH
LH
H
X
X
V V VLL
LL
H
X
X
XX
XLH
HH
H
X
X
XX
XLH
HL
H
X
X
XX
XHX
XX
H
H
X
X X XLL
LH
H
L
X
X X XLL
LH
L
H
X
XX
XHX
XX
LH HX
H
L
X
XX
XXX
XX
L
H
X
XX
XXX
XX
H
L
X
X X XHX
XX
LH HH
L
H
X
X X XHX
XX
LH HL
H
X
L
X X XXX
XX
H
X
H
XX
XXX
XX
Notes
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level.
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the
commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Address Input for Mode Set (Mode Register Operation)
5. Power Down Mode can not be entered during a burst cycle. When this command is asserted during a burst
cycle the device enters Clock Suspend Mode.
INFINEON Technologies AG
8
2002-12-20