HYB39L256160AC Datasheet, PDF (12/48 Pages) Infineon Technologies AG – 256 MBit Synchronous Low-Power DRAM

HYB 39L256160AC / T
256MBit 3.3V Mobile-RAM
command is necessary. A minimum t_RC time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access command after the automatic refresh operation.
In Auto-Refresh mode all banks are refreshed, independed if the partial activation has been set.
Self-Refresh
The chip has an on-chip timer that is used when the Self Refresh mode is entered. The self-refresh
command is asserted with RAS, CAS, and CKE low and WE high at a clock edge. All external
control signals including the clock are disabled. Returning CKE to high enables the clock and
initiates the refresh exit operation. After the exit command, at least one t_RC delay is required prior to
any command. After self refresh exit an autorefresh command is recommended due to the chance
of an exit just before the next internal refresh is executed.
DQM Function
DQMx has two functions for data I/O read and write operations. During reads, when it turns to “high”
at a clock edge, data outputs are disabled and become high impedance after two clock periods
(DQM Data Disable Latency t_DQZ). It also provides a data mask function for writes. When DQM is
activated, the write operation at the next clock is prohibited (DQM Write Mask Latency t_DQW = zero
clocks).
Suspend Mode
During normal access, CKE is held high enabling the clock. When CKE is low, it freezes the internal
clock and extends data read and write operations. One clock delay is required for mode entry and
exit (Clock Suspend Latency t_CSL).
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks must be
precharged before the Mobile-RAM can enter the Power Down mode. Once the Power Down mode
is initiated by holding CKE low, all receiver circuits except for CLK and CKE are gated off. The
Power Down mode does not perform any refresh operations, therefore the device can’t remain in
Power Down mode longer than the Refresh period (t_REF) of the device. Exit from this mode is
performed by taking CKE “high”. One clock delay is required for power down mode entry and exit.
Auto Precharge
Two methods are available to precharge Mobile-RAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function
is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function
is initiated. The Mobile-RAM automatically enters the precharge operation after t_WR (Write recovery
time) following the last data in.
INFINEON Technologies AG
12
2002-12-20