HYB39L256160AC Datasheet, PDF (1/48 Pages) Infineon Technologies AG – 256 MBit Synchronous Low-Power DRAM

HYB 39L256160AC / T
256MBit 3.3V Mobile-RAM
256 MBit Synchronous Low-Power DRAM
Data Sheet Revision Dec. 2002
Features
f_CK,MAX
t_CK3,MIN
t_AC3,MAX
t_CK2,MIN
t_AC2,MAX
-7.5 -8
Units
133 125 MHz
7.5 8
ns
5.4 6
ns
9.5 9.5 ns
6
6
ns
• 16Mbit x16 organisation
• VDD = VDDQ = 3.3 V
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3
• Programmable Wrap Sequence: Sequential
or Interleave
• Automatic and Controlled Precharge
Command
• Programmable Burst Length: 1, 2, 4, 8 and
full page
• Data Mask for byte control
• Auto Refresh (CBR)
• 8192 Refresh Cycles / 64ms
• Very low Self Refresh current
• Power Down and Clock Suspend Mode
• Random Column Address every CLK
(1-N Rule)
• P-TFBGA-54, with 9 x 6 ball array with
3 depopulated rows, 12 x 8 mm²
• P-TSOPII-54 alternate package
• Operating Temperature Range
Commerical (0⁰ to 70⁰C)
Description
The HYB 39L256160AC Mobile-RAM is a new generation of low power, four bank Synchronous
DRAM’s organized as 4 banks x 4Mbit x 16. These synchronous Mobile-RAMs achieve high speed
data transfer rates by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS
latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. The device operates with a single
3.3V ±0.3V power supply.
Compared to conventional SDRAM the self-refresh current is further reduced. The Mobile-RAM
devices are available in FBGA “chip-size” or TSOPII packages.
INFINEON Technologies AG
1
2002-12-20