HYB39L256160AC Datasheet, PDF (5/48 Pages) Infineon Technologies AG – 256 MBit Synchronous Low-Power DRAM

Functional Block Diagrams
HYB 39L256160AC / T
256MBit 3.3V Mobile-RAM
Column Address
Counter
Column Addresses
A0 - A8, AP,
BA0, BA1
Column Address
Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh Counter
Row
Decoder
Memory
Array
Bank 0
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 1
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 2
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 3
8192 x 512
x 16 Bit
Input Buffer Output Buffer
DQ0 - DQ15
Control Logic &
Timing Generator
Block Diagram: 16Mb x16 SDRAM (13 / 9 / 2 addressing)
SPB04124
INFINEON Technologies AG
5
2002-12-20