HYB39L256160AC Datasheet, PDF (18/48 Pages) Infineon Technologies AG – 256 MBit Synchronous Low-Power DRAM

HYB 39L256160AC / T
256MBit 3.3V Mobile-RAM
Notes
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests are referenced to the 0.9V crossover point. The transition time is measured
between V_IH and V_IL. All AC measurements assume t_T = 1 ns with the AC output load circuit
(details will be defined later). Specified t_AC and t_OH parameters are measured with a 30pF only,
without any resistive termination and with a input signal of 1V/ns edge rate.
I/O
30 pF
Measurement conditions for
t_AC and t_OH
3. If clock rising time is longer than 1 ns, a time (t_T/2 - 0.5) ns has to be added to this parameter.
4. If t_T is longer than 1 ns, a time (t_T - 1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole
number)
6. Access time from clock t_AC is 4.6ns for -7.5 components with no termination and 0pF load,
Data out hold time t_OH is 1.8ns for -7.5 components with no termination and 0pF load.
7. The write recovery time of t_WR = 14ns cycles allows the use of one clock cycle for the write
recovery time when the memory operation frequency is equal or less than 72MHz. For all
memory operation frequencies higher than 72MHz two clock cycles for t_WR are mandatory.
INFINEON recommends to use two clock cylces for the write recovery time in all applications.
INFINEON Technologies AG
18
2002-12-20