TLE82453-3SA_15 Datasheet, PDF (57/71 Pages) Infineon Technologies AG – 3 Channel High-Side and Low-Side Linear Solenoid Driver IC

TLE82453-3SA
SPI Registers
12.5
CLK-DIVIDER REGISTER
CLK-DVD
Clock Divider Register
Reset Value: 0300 0818_H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R/W 0
0
0
0
0
1
1
not used
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
not used
WDEN
M
N
Fsys div
Field
Bits
R/W
31
WDEN
12
M
11:6
N
5:2
Fsys div 1:0
Type
rw
rw
rw
rw
rw
Description
Read / Write bit
0 = Read
1 = Write
When reading the register, the R/W bit is 0
Enable CLK pin watchdog
0 = Disable Watchdog (Reset value)
1 = Enable Watchdog
The output stages are disabled until the WDEN bit is set. To operate
the device without the watchdog function, the WDEN bit must be set
to 1 and then cleared to 0.
Set mantissa of pre-divider (Reset value = 32 decimal)
Fdither = Fsys / ((M+1) * 2^N)
Set exponent of pre-divider (Reset value = 6)
Fdither = Fsys / ((M+1) * 2^N)
Set F_CLK / F_SYS divider
00 - divide by 8 (Reset value)
01 - divide by 6
10 - divide by 4
11 - divide by 2
Note: Autozero should be initiated after changing the divider, first
write to this register after powerup automatically starts the autozero
process
Note: Following a reset or power-up event, the outputs are disabled until this register has been written to.
Data Sheet
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57
Rev 1.0, 2015-03-27