TLE82453-3SA_15 Datasheet, PDF (36/71 Pages) Infineon Technologies AG – 3 Channel High-Side and Low-Side Linear Solenoid Driver IC

JUNCTION
TEMP
Tj < OTSD
Tj > OTSD
TLE82453-3SA
Protection Functions
Tj < OTSD
I_LOADx
VLOADx
OTx
CSN
SI
SO
FAULTN
(FMx = 1)
DIAG-
NOSIS
DIAG-
NOSIS
OTx = 0
DIAG- DIAG-
NOSIS NOSIS
DIAG- DIAG-
NOSIS NOSIS
OTx=1 OTx=1
DIAG- DIAG-
NOSIS NOSIS
DIAG- DIAG-
NOSIS NOSIS
OTx=1 OTx=0
I > 0ma
Figure 16 Overtemperature Timing Diagram (Low-Side Configuration)
9.4
Overvoltage Shutdown
This feature is implemented to protect the internal power transistors from damage due to overvoltage on the VBAT
pin. If the voltage on the VBAT pin exceeds the VBAT overvoltage threshold an overvoltage fault bit will be set in
the diagnostic register. This fault bit will be latched until the diagnostic register is read by SPI and the overvoltage
condition no longer exists. All channels are disabled while the overvoltage condition exists and the setpoints and
EN bits of all the channels are cleared to 0, and the fault bit is latched in the diagnostic register. The channel will
remain disabled until the diagnostic register is read and the EN bit is set back to 1 and the setpoint is set to >0.
The charge pump output voltage is clamped to approximately 50V. The charge pump undervoltage fault (CPUV)
may be set before the VBAT overvoltage fault bit is set depending on the rise time of the VBAT voltage.
Data Sheet
-
36
Rev 1.0, 2015-03-27