TLE82453-3SA_15 Datasheet, PDF (19/71 Pages) Infineon Technologies AG – 3 Channel High-Side and Low-Side Linear Solenoid Driver IC

TLE82453-3SA
Power Supply
Apply +5V to each
VDDx pin and the
VIO pin
FAULTN Pin = LOW
Apply the clock signal to the CLK
pin, then transition the RESN pin
from low to high.
T_POR /ms = 65536/(F_CLK/kHz)
see P_6.12.20
FAULTN Pin = LOW
Wait for the T_POR timer to elapse
The SPI bus will begin responding
after the T_POR has elapsed.
FAULTN Pin = LOW
Write to the CLK-DIVIDER register
via the SPI interface.
Enable the watchdog and set the
system clock divider.
T_WU /ms = 65536/(F_SYS/kHz) + 0.1
see P_6.12.14
FAULTN Pin = HIGH
Wait for T_WU wake up timer to
elapse
T_WU has elapsed when the AZ bit
returns to 1 in the SPI register.
FAULTN Pin = HIGH
Device is ready to
operate
Figure 5 Initialization Sequence
Data Sheet
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19
Rev 1.0, 2015-03-27