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TLE82453-3SA_15 Datasheet, PDF (18/71 Pages) Infineon Technologies AG – 3 Channel High-Side and Low-Side Linear Solenoid Driver IC
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TLE82453-3SA
Power Supply
VDDD
< VDDx_UV
X
X
> VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV
VDDA
X
< VDDx_UV
X
> VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV
VDDAREF
X
X
< VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV > VDDx_UV
RESN
X
X
X
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
CLK
X
X
X
X
TCLK >
TCLK_MSS
TCLK >
TCLK_MSS
TCLK <
TCLK_MSS
TCLK <
TCLK_MSS
TCLK <
TCLK_MSS
TCLK <
TCLK_MSS
TCLK <
TCLK_MSS
TCLK <
TCLK_MSS
VIO
X
X
X
X
> 3.0V
> 3.0V
0V
> 3.0V
> 3.0V
> 3.0V
> 3.0V
> 3.0V
WDEN
X
X
X
X
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
EN
X
X
X
X
X
X
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
VCPOUT -
VBAT
X
X
X
X
X
X
> CPUV
X
< CPUV
> CPUV
> CPUV
> CPUV
VBAT
X
X
X
X
X
X
< VBATOV
X
X
> VBATOV < VBATOV < VBATOV
VLSUPX
X
X
X
X
X
X
> VLSUPUV
X
X
X
< VLSUPUV > VLSUPUV
Sleep Mode
Watchdog
Fault
Channel
Operational
SPI
Functional
Diagnostics
Functional
FAULTN
RST bit
YES
NO
NO
NO
NO
LOW
HIGH (2)
YES
NO
NO
NO
NO
LOW
HIGH (2)
YES
NO
NO
NO
NO
LOW
HIGH (2)
NO
NO
NO
NO
NO
LOW
HIGH (2)
NO
NO
NO
YES
NO
LOW
HIGH (3)
NO
NO
NO
NO
YES
NO
NO
NO
NO
YES
NO
NO
Response is ICVID
NO
INPUT – YES
Response is 0000 H
YES
YES
NO Load faults
are detected
LOW
Undefined
LOW (1)
NO
YES
YES
LOW
HIGH (3)
unchanged
unchanged
unchanged
NO
NO
NO
NO
NO
NO
NO
YES
NO
(Channel X only)
YES
YES
YES
YES
YES
YES
LOW
LOW (4)
HIGH
unchanged
unchanged
unchanged
Figure 4 Power Supply Mode Diagram
The X's indicate a don't care condition for all the states below the double line.
1. The FAULTN pin is LOW if the FME fault mask bit is set to 1
2. The RST bit in the DIAGNOSIS register will be set after the device exits the reset state
3. A missing CLK signal will result in a reset only if the CLK Watchdog has been enabled
4. The FAULTN pin is LOW if the FMx fault mask bit is set to 1
6.11
Initialization
The following figure illustrates the initialization sequence for the device after power-up. The TPOR cycle begins on
the first CLK clock cycle after the RESN pin transitions from low to high.
Data Sheet
-
18
Rev 1.0, 2015-03-27
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