PXB4360F Datasheet, PDF (51/66 Pages) Infineon Technologies AG – ICs for Communications

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The system clock is passed to CAME at the CLK input. For typical applications, it will be equal
to ALP SYS_CLK/2 = 25.92 MHz. This is the only clock supply for the CAME (if the BSCAN
interface clock is ignored). It determines operation of the bus interface and the timing of all
clocked internal functions. The ALP delivers the CLK signal for the CAME without any glue logic,
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The RESET signal is an active low input. As long as it is connected to a low level, the data bus
DAT(32..0) will be forced to a high-impedance state, CO(2..0) are set to 000. TDO and
TMD(7..0) are not influenced.
When the transition low → high is detected at RESET, the internal control logic is reset, the
internal status is “ok” and all test function registers are set to their default values as outlined in
section 5.7 on page 37. Thus, test multiplexer selection and the CO(2..0) outputs are
influenced. Internal registers around the memory array are also cleared. The contents of the
memory array are not changed intentionally, but memory protection during reset is not
implemented.
As long as RESET stays at a high level, normal operation will occur.
Data Sheet
6-51
07.2000