PXB4360F Datasheet, PDF (47/66 Pages) Infineon Technologies AG – ICs for Communications

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For single chip applications, the CAME device must be configured as master by CA and the
CI(1..0) inputs must be supplied with low level, pretending an “always mismatch” condition of the
non-existent slave. The CI(2) input is not evaluated by a chip configured as master, but it needs
connection to ground.
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0
Device is master, its LCI range is 0..8191
input
1
Device is slave, its LCI range is 8192..16383
CI(1..0) 00
A search request (#1..3 or #4 with MODE.CEE= 1) is running input
with the result mismatch on the opposite chip
01
A search request (#1..3 or #4 with MODE.CEE= 1) is running
with the result of single match or multimatch on the opposite chip
10
No request is processed by the opposite chip
11
Request #4..6 is processed by the opposite chip
CI(2) 0
CI(2) is ignored by a master.
A slave interprets CI(2) as follows:
Data output at DAT is prohibited in read cycles
input
1
Data output at DAT is allowed in read cycles
CO(1..0) 00
A search request (#1..3 or #4 with MODE.CEE= 1) is running output
with the result mismatch
01
A search request (#1..3 or #4 with MODE.CEE= 1) is running
with the result of single match or multimatch
10
No request is processed
11
Request #4..6 is processed
CO(2) 0
CO(2) of a slave is undefined.A master outputs CO(2) as
follows:
Prohibit data output of a slave in read cycles
output
1
Allow data output of a slave in read cycles
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If two CAME chips are cascaded, the selection of which device will react and may respond is
made based on the command started. No additional preparation at the bus interface is
necessary. In read or write command cycles, the LCI - at least part of the command word -
Data Sheet
6-47
07.2000