PXB4360F Datasheet, PDF (40/66 Pages) Infineon Technologies AG – ICs for Communications

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Disturbed Parity Generation.
Generate a bus parity error in the read access at the end of this command cycle.
This bit is automatically reset. DPG is not supported by the ALP!
0
Default
&,2
CI(2) / CO(2) data
If this bit is written, it determines the setting of the CO(2) output while it is used for
Cascade Interface check. If it is read, it reflects the level at the CI(2) input.
y
Default
y depends on the CI input with the same index
&,2
CI(1) / CO(1) data
If this bit is written, it determines the setting of the CO(1) output while it is used for
cascade interface check. If it is read, it reflects the level at the CI(1) input.
y
Default
y depends on the CI input with the same index
&,2
CI(0) / CO(0) data
If this bit is written, it determines the setting of the CO(0) output while it is used for
Cascade Interface check. If it is read, it reflects the level at the CI(0) input.
y
Default
y depends on the CI input with the same index
&/(
Check of a Line before write Enable.
This means writing of a valid entry (with its VCON bit set to 1) over a valid entry in
memory (also with VCON bit contained in this line set to 1) is not performed;
instead, in the status field, an alarm is returned. Activation of this bit prolongs the
write request (restricted usage in 622 Mbit/s systems). CLE is not supported by the
ALP!
0
Default
&((
Check of an Entry before write Enable.
Search is performed for occurrence of write pattern in the CAME (and a cascaded
CAME, if connected). If the pattern is already present, the related line will not be
updated and an alarm is returned in the status field. Activation of this bit prolongs
the write request (restricted usage in 622 Mbit/s systems). CEE is not supported by
the ALP!
0
Default
Data Sheet
5-40
07.2000