PXB4360F Datasheet, PDF (19/66 Pages) Infineon Technologies AG – ICs for Communications

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The PXB 4360 F is a Content Addressable Memory Element (CAME) that searches for a
programmable 32-bit pattern the corresponding programmable 14-bit pattern; or vice versa.
Additionally, two search bits are provided to support the search for unused entries and to support
the search for F4-OAM connections in ATM. One CAME supports up to 8192 entries. This can
be extended up to 16384 entries by adding a second, cascaded CAME, without the need for
additional glue logic.
The target application of the CAME is the Address Reduction mechanism for ATM cells
performed by the Infineon ATM layer chip ALP PXB 4350. The ALP extracts the Virtual Path
Identifier of a standardized ATM cell (VPI) and the Virtual Channel Identifier of a standardized
ATM cell (VCI) from the ATM Cell Header and sends them together with the Port Number as a
32-bit pattern to the CAME. After the search procedure of the CAME, the corresponding 14-Bit
pattern is sent back to the ALP. The 14-bit pattern is used as a Local Connection Identifier (LCI)
inserted into the ATM Cell Header. Herewith, the CAME translates any arbitrary address, within
the address range of 2³², into another arbitrary address within the address range of 2¹³ (or 2¹⁴ if
two CAME chips are cascaded). The entire search process is completed during one ATM cell
cycle with a bit rate of 686 MBit/s.
Data Sheet
3-19
07.2000