PXB4360F Datasheet, PDF (39/66 Pages) Infineon Technologies AG – ICs for Communications

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For request #1, the VSET portion for comparison is LQWHUQDOO\ set to 1, VPED is set to 0 and
VCED set to 1. In request #2, the settings VSET = 1, VCED = 0 and VPED = 0 are used. For
request #3, all three VSET, VCED and VPED DUH SURJUDPPDEOH in the MODE register. Both
modes of searching as well as searching for invalid lines are possible under microprocessor
control during cell processing.
For SW convenience and acceleration of the connection data update, write request #4 may be
extended by using the CEE and CLE bits in the MODE register. If CEE is set to 1 before writing
a pattern to a line, searching for this pattern in the CAME (and the optional second CAME) is
performed. If this pattern is already present, the command cycle is finished without writing to the
line. This failure is reported in the status register. Next, if enabled, prior to writing with CLE set
to 1, the destination line is checked to determine if it already contains a valid entry (with VCON
= 1). Writing is prevented only if a valid pattern (VCON =1) is intended to be written over a valid
entry and the failure is reported in the status field.
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VPED
VSET
DPG
CIO2
CIO1
CIO0

VCED

CLE
CEE
9&('
VCI Evaluation Disable.
This bit has no influence on any requests except request #3:
0
Default
1
VCI is ignored in search requests of type #3.
93('
VPI Evaluation Disable.
This bit has no influence on any requests except request #3:
0
Default
1
PN / VPI is ignored in search requests of type #3.
96(7
For VCON comparison internally Set value for search request #3:
0
Free empty lines are localized.
1
Default
Data Sheet
5-39
07.2000