PXB4360F Datasheet, PDF (41/66 Pages) Infineon Technologies AG – ICs for Communications

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TMODE register use is allowed only if the MODE register is set to the default values mentioned
in VHFWLRQ  on page 39. The TMODE register bits cause the following functional changes:

reserved(4:0)
TWE
TRE

reserved(5)

TSE
UHVHUYHG  Reserved, do not activate.
000000 Default
7:(
Test Write Enable.
Enables writing to all memory banks in parallel. This bit changes a write
request #4 to a “test write” request.
0
Default
75(
Test Read Enable.
Enables parallel reading from all banks at the same offset. This bit changes a
read request #5 to a “test read” request.
0
Default
76(
Test Search Enable.
Enables parallel comparing in all banks. This bit changes a search request #3
to a “test search” request.
0
Default
Data Sheet
5-41
07.2000