English
Language : 

ICB2FL03G Datasheet, PDF (36/60 Pages) Infineon Technologies AG – 2nd Generation FL Controller for Fluorescent Lamp Ballasts
ICB2FL03G
Controller for Fluorescent Lamp Ballasts
Functional Description
2.8.3 Built-in Customer Test Mode (Clock Acceleration)
The built-in customer test mode, supported by this IC, saves testing time for customers in terms of ballast end test.
In this mode, the IC accelerates the internal clock in order to reduce the time of the 4 different procedures by the
following factors (see Table 2).
Table 2 Specified Acceleration Factors
Phase
Duration for Test [ms]
Preheating
625
Time Out Ignition
118.5
Pre Run Mode
41.7
EOL2
41.7
Acceleration Factor
4
2
15
60
Nominal Duration [ms]
2500 (max)
237
625
2500
2.8.3.1 Enabling of the Clock Acceleration
The clock acceleration (Built-in Customer Test Mode) is activated when the chip supply voltage exceeds VCC
> 14.0 V and the voltages at the run and preheating frequency pins are set to VRFRUN = VRFPH = 5.0 V (± 5 %) –
see Figure 33. A RES pin voltage of VRES > 3.5 V up to 5.0 V (± 5 %) prevents a power-up of the IC, the IC remains
in a mode before powering up as long as the voltage at the RES pin is VRES > 3.5 V up to 5.0 V (± 5 %) – no power-
up.
Note: After the activation of the clock acceleration mode, the voltage level of 5.0 V at the run and preheating
frequency pins (VRFRUN = VRFPH) can be released.
2.8.3.2 Starting the Chip with Accelerated Clock
In order to start the IC with an accelerated clock, set the voltage at the RES pin to GND (VRES = 0 V), see
Figure 33. The IC powers up the system and starts working with an accelerated clock. The duration of the different
modes are accelerated by the factors shown in Table 2.
Enabling of
Clock
Acceleration
VCC
VCCNom
14.0 V
Filament
Detection
10.6 V
VR FR U N
5.0 V
2.5 V
V R FP H
5.0 V
2.5 V
Starting the Chip with
an accelerated Clock
VRES
3.5 V
IC Powers UP
IC Remains
in Power UP
Propagation Accelerated
Delay Pre Heating
by Factor 4
Accelerated
Ign. Time OUT
by Factor 2
Accelerated
Pre RUN
by Factor 15
Accelerated
EOL2
by Factor 60
in Run Mode
Time
Time
Time
Time
Figure 33 Clock Acceleration (Built in Customer Test Mode)
Final Data Sheet
36
V1.1, 2013-08-14