ICB2FL03G Datasheet, PDF (14/60 Pages) Infineon Technologies AG – 2nd Generation FL Controller for Fluorescent Lamp Ballasts

ICB2FL03G
Controller for Fluorescent Lamp Ballasts
Functional Description
HSGD (high-side gate drive, pin 16)
The gate of the high-side MOSFET in a half-bridge inverter topology is controlled by this pin. There is an active
L-level during UVLO and limitation of the max H-level at 11.0 V during normal operation. The switching
characteristics are the same as described for LSGD (pin 1). It is recommended to use a resistor of about 10 Ω
between the drive pin and gate in order to avoid oscillations and in order to shift the power dissipation of
discharging the gate capacitance into this resistor. The dead time between LSGD signal and HSGD signals is
self-adapting between 1.05 μs and 2.1 μs (typically).
2
Functional Description
This section describes applications and functionality of the chip.
2.1
Typical Application Circuitry
The schematic shown in Figure 3 shows a typical application for a T5 single fluorescent lamp. It is designed for
universal input voltage from 90 V_AC up to 270 V_AC. The following sections explain the components in reference to
this schematic.
L101 D1...4
C1
90 ...
270 VAC
C2
R41
L1
R34
D5 ^R13
R14
R1 _Q1
R15
R2
R16
C10
R11
PFCZCD
PFCGD
PFCVS
PFCCS
R12
R35
Q2
R26
HSGD
HSVCC
HSGND
C14
Q3
R27
LSGD
LSCS
D6
R18 C11 R20
R30
DR12
D9
C12
R21R22R23
C13
R25
R42 R43 R44
C40
L2
R45
C17
C15
C24
C16
R36
D7
D8
C19
Figure 3 Application Circuit of Ballast for a Single Fluorescent Lamp (FL)
2.2
Normal Startup
This section describes the basic operation flow (8 phases) from the UVLO (Under Voltage Lock Out) into run mode
without any error detection. For detailed information see Section 2.2.1 and Section 2.2.2. Figure 4 shows the 8
different phases during a typical start from UVLO (phase 1, Figure 4) to run mode (phase 8, Figure 4) and then
into normal operation (no failure detected).
If the AC line input is switched ON, the V_CC voltage rises to the UVLO threshold V_CC = 10.6 V (no IC activity during
UVLO). If V_CC exceeds the first threshold of V_CC = 10.6 V, the IC starts the first level of detection activity, the high
and low side filament detection during the start-up hysteresis (phase 2, Figure 4).
Final Data Sheet
14
V1.1, 2013-08-14