71V3558S200PFG Datasheet, PDF (9/28 Pages) Integrated Device Technology – 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table ⁽¹⁾
CEN R/W
Chip⁽⁵⁾
Enable
ADV/LD BWx
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(2 cycles later)
L
L
Select
L
Valid
External
X
LOAD WRITE
D⁽⁷⁾
L
H
Select
L
X
External
X
LOAD READ
Q⁽⁷⁾
L
X
X
H
Valid
Internal
LOAD WRITE /
BURST WRITE
D⁽⁷⁾
BURST WRITE
(Advance burst counter)⁽²⁾
L
X
X
H
X
Internal
LOAD READ /
BURST READ
Q⁽⁷⁾
BURST READ
(Advance burst counter)⁽²⁾
L
X Deselect
L
X
X
X
DESELECT or STOP⁽³⁾
HiZ
L
X
X
H
X
X
DESELECT / NOOP
NOOP
HiZ
H
X
X
X
X
X
X
SUSPEND⁽⁴⁾
Previous Value
NOTES:
5281 tbl 08
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst
cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state
two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/Os remains
unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes ⁽¹⁾
OPERATION
READ
WRITE ALL BYTES
WRITE BYTE 1 (I/O[0:7], I/OP1)⁽²⁾
WRITE BYTE 2 (I/O[8:15], I/OP2)⁽²⁾
WRITE BYTE 3 (I/O[16:23], I/OP3)^(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4)^(2,3)
NO WRITE
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
R/W
BW1
BW2
BW3⁽³⁾
BW4⁽³⁾
H
X
X
X
X
L
L
L
L
L
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
H
H
H
H
5281 tbl 09
6.942