71V3558S200PFG Datasheet, PDF (14/28 Pages) Integrated Device Technology – 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with CHIP Enable Used ⁽¹⁾
Cycle
Address
R/W ADV/LD
CE⁽²⁾
CEN
BWx
OE
I/O^{(3) Comments}
n
X
X
L
H
L
X
X
? Deselected.
n+1
X
X
L
H
L
X
X
? Deselected.
n+2
A0
H
L
L
L
X
X
Z Address and Control meet setup
n+3
X
X
L
H
L
X
X
Z Deselected or STOP.
n+4
A1
H
L
L
L
X
L
Q0 Address A0 Read out. Load A1.
n+5
X
X
L
H
L
X
X
Z Deselected or STOP.
n+6
X
X
L
H
L
X
L
Q1 Address A1 Read out. Deselected.
n+7
A2
H
L
L
L
X
X
Z Address and control meet setup.
n+8
X
X
L
H
L
X
X
Z Deselected or STOP.
n+9
X
X
L
H
L
X
L
Q2 Address A2 Read out. Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
5281 tbl 19
Write Operation with Chip Enable Used ⁽¹⁾
Cycle
Address
R/W ADV/LD CE⁽²⁾
CEN BWx
OE
n
X
X
L
H
L
X
X
n+1
X
X
L
H
L
X
X
n+2
A0
L
L
L
L
L
X
n+3
X
X
L
H
L
X
X
n+4
A1
L
L
L
L
L
X
n+5
X
X
L
H
L
X
X
n+6
X
X
L
H
L
X
X
n+7
A2
L
L
L
L
L
X
n+8
X
X
L
H
L
X
X
n+9
X
X
L
H
L
X
X
I/O^{(3) Comments}
? Deselected.
? Deselected.
Z Address and Control meet setup
Z Deselected or STOP.
D0 Address D0 Write in. Load A1.
Z Deselected or STOP.
D1 Address D1 Write in. Deselected.
Z Address and control meet setup.
Z Deselected or STOP.
D2 Address D2 Write in. Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
5281 tbl 20
6.1442