71V3558S200PFG Datasheet, PDF (11/28 Pages) Integrated Device Technology – 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles ⁽²⁾
Cycle
Address
R/W ADV/LD CE⁽¹⁾ CEN BWx
OE
I/O Comments
n
A0
H
L
L
L
X
X
X Load read
n+1
X
X
H
X
L
X
X
X Burst read
n+2
A1
H
L
L
L
X
L
Q0 Load read
n+3
X
X
L
H
L
X
L
Q0+1 Deselect or STOP
n+4
X
X
H
X
L
X
L
Q1 NOOP
n+5
A2
H
L
L
L
X
X
Z Load read
n+6
X
X
H
X
L
X
X
Z Burst read
n+7
X
X
L
H
L
X
L
Q2 Deselect or STOP
n+8
A3
L
L
L
L
L
L
Q2+1 Load write
n+9
X
X
H
X
L
L
X
Z Burst write
n+10
A4
L
L
L
L
L
X
D3 Load write
n+11
X
X
L
H
L
X
X
D3+1 Deselect or STOP
n+12
X
X
H
X
L
X
X
D4 NOOP
n+13
A5
L
L
L
L
L
X
Z Load write
n+14
A6
H
L
L
L
X
X
Z Load read
n+15
A7
L
L
L
L
L
X
D5 Load write
n+16
X
X
H
X
L
L
L
Q6 Burst write
n+17
A8
H
L
L
L
X
X
D7 Load read
n+18
X
X
H
X
L
X
X
D7+1 Burst read
n+19
A9
L
L
L
L
L
L
Q8 Load write
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
5281 tbl 12
Read Operation ⁽¹⁾
Cycle
Address
R/W ADV/LD CE⁽²⁾ CEN BWx
OE
n
A0
H
L
L
L
X
X
n+1
X
X
X
X
L
X
X
n+2
X
X
X
X
X
X
L
I/O Comments
X Address and Control meet setup
X Clock Setup Valid
Q0 Contents of Address A0 Read Out
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
5281 tbl 13
61.412