71V3558S200PFG Datasheet, PDF (15/28 Pages) Integrated Device Technology – 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
Parameter
Test Conditions
Min.
Max. Unit
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
___
5
µA
|ILI|
LBO, JTAG and ZZ Input Leakage Current⁽¹⁾
VDD = Max., VIN = 0V to VDD
___
30
µA
|ILO|
Output Leakage Current
VOUT = 0V to VDDQ, Device Deselected
___
5
µA
VOL
Output Low Voltage
IOL = +8mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
___
V
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled if they are not actively driven in the application.
5281 tbl 21
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range ⁽¹⁾ (VDD = 3.3V +/-5%)
200MHz⁽⁴⁾
166MHz
133MHz
Symbol
Parameter
Test Conditions
Com'l Only Com'l Ind Com'l Ind
IDD _{Operating Power}
Supply Current
Device Selected, Outputs Open,
ADV/LD = X, VDD = Max.,
VIN > VIH or < VIL, f = fMAX⁽²⁾
400
350 360 300 310
ISB1 _{CMOS Standby}
Device Deselected, Outputs Open,
40
Power Supply Current ^{VDD = Max., VIN > VHD or < VLD, f}
= 0^(2,3)
40
45
40
45
ISB2 _{Clock Running Power} Device Deselected, Outputs Open,
130
Supply Current
VDD = Max., VIN > VHD or < VLD, f
= fMAX^(2.3)
120 130 110 120
ISB3 _{Idle Power}
Supply Current
Device Selected, Outputs Open,
CEN > VIH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX^(2,3)
40
40
45
40
45
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
4. Only available in 256K x 18 configuration.
100MHz
Com'l Ind Unit
250 255 mA
40
45 mA
100 110 mA
40
45 mA
5281 tbl 22
AC Test Loads
I/O
6
5
4
ΔtCD ³
(Typical, ns)
2
VDDQ/2 ^{AC Test Conditions}
50Ω
(VDDQ = 3.3V)
Input Pulse Levels
Z0 = 50Ω
, _{Input Rise/Fall Times}
5281 drw 04
Figure 1. AC Test Load
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1
20 30 50 80 100
Capacitance (pF)
, ₂₀₀
5281 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
61.452
0 to 3V
2ns
1.5V
1.5V
See Figure 1
5281 tbl 23