71V3558S200PFG Datasheet, PDF (16/28 Pages) Integrated Device Technology – 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
200MHz⁽⁶⁾
166MHz
133MHz
100MHz
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC
Clock Cycle Time
5
____
6
____
7.5
____
10
____
ns
tF⁽¹⁾
Clock Frequence
____
200
____
166
____
133
____
100 MHz
tCH⁽²⁾
Clock High Pulse Width
1.8
____
1.8
____
2.2
____
3.2
____
ns
tCL⁽²⁾
Clock Low Pulse Width
1.8
____
1.8
____
2.2
____
3.2
____
ns
Output Parameters
tCD
Clock High to Valid Data
____
3.2
____
3.5
____
4.2
____
5
ns
tCDC
Clock High to Data Change
1
____
1
____
1
____
1
____
ns
tCLZ^(3,4,5)
Clock High to Output Active
1
____
1
____
1
____
1
____
ns
tCHZ^(3,4,5)
Clo ck High to Data High-Z
1
3
1
3
1
3
1
3.3
ns
tOE
Output Enable Access Time
____
3.2
____
3.5
____
4.2
____
5
ns
tOLZ^(3,4)
Output Enable Low to Data Active
0
____
0
____
0
____
0
____
ns
tOHZ^(3,4)
Output Enable High to Data High-Z
____
3.5
____
3.5
____
4.2
____
5
ns
Set Up Times
tSE
Clock Enable Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSA
Address Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSD
tSW
tSADV
Data In Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
Read/Write (R/W) Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
Advance/Load (ADV/LD) Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSC
Chip Enable/Select Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
tSB
Byte Write Enable (BWx) Setup Time
1.5
____
1.5
____
1.7
____
2.0
____
ns
Hold Times
tHE
Clock Enable Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHD
tHW
tHADV
Data In Hold Time
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
0.5
____
0.5
____
ns
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHB
Byte Write Enable (BWx) Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
NOTES:
5281 tbl 24
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage. The
specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ, which is a
Max. parameter (worse case at 70 deg. C, 3.135V).
6. Commercial temperature range only. Only available in 256K x 18 configuration.
6.1462