71V3558S200PFG Datasheet, PDF (22/28 Pages) Integrated Device Technology – 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
tJF
TCK
tJCYC
tJR
tJCL
tJCH
Device Inputs⁽¹⁾/
TDI/TMS
Device Outputs⁽²⁾/
TDO
tJS tJH
tJRSR
tJDC
tJCD
TRST⁽³⁾
tJRST
x
M5281 drw 01
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics^(1,2,3,4)
Symbol
tJ CYC
tJCH
tJCL
tJR
tJF
tJRST
tJ RSR
tJCD
tJDC
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
Min.
100
40
40
____
____
50
50
____
0
Max.
____
____
____
5⁽¹⁾
5⁽¹⁾
____
____
20
____
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
JTAG Identification (JIDR)
32
Boundary Scan (BSR)
Note (1)
I5281 tbl 03
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
tJS
JTAG Setup
25
____
ns
tJH
JTAG Hold
25
____
ns
I5281 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.2422