71V3558S200PFG Datasheet, PDF (13/28 Pages) Integrated Device Technology – 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used ⁽¹⁾
Cycle
Address
R/W ADV/LD CE⁽²⁾ CEN BWx
OE
I/O Comments
n
A0
H
L
L
L
X
X
X Address and Control meet setup
n+1
X
X
X
X
H
X
X
X Clock n+1 Ignored
n+2
A1
H
L
L
L
X
X
X Clock Valid
n+3
X
X
X
X
H
X
L
Q0 Clock Ignored. Data Q0 is on the bus.
n+4
X
X
X
X
H
X
L
Q0 Clock Ignored. Data Q0 is on the bus.
n+5
A2
H
L
L
L
X
L
Q0 Address A0 Read out (bus trans.)
n+6
A3
H
L
L
L
X
L
Q1 Address A1 Read out (bus trans.)
n+7
A4
H
L
L
L
X
L
Q2 Address A2 Read out (bus trans.)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
5281 tbl 17
Write Operation with Clock Enable Used ⁽¹⁾
Cycle
Address
R/W ADV/LD CE⁽²⁾ CEN BWx
OE
I/O
n
A0
L
L
L
L
L
X
X
n+1
X
X
X
X
H
X
X
X
n+2
A1
L
L
L
L
L
X
X
n+3
X
X
X
X
H
X
X
X
n+4
X
X
X
X
H
X
X
X
n+5
A2
L
L
L
L
L
X
D0
n+6
A3
L
L
L
L
L
X
D1
n+7
A4
L
L
L
L
L
X
D2
Comments
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
Clock Ignored.
Clock Ignored.
Write Data D0
Write Data D1
Write Data D2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
5281 tbl 18
61.432