71V3558S200PFG Datasheet, PDF (1/28 Pages) Integrated Device Technology – 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

128K x 36, 256K x 18
IDT71V3556S/XS
3.3V Synchronous ZBT SRAMs IDT71V3558S/XS
3.3V I/O, Burst Counter
IDT71V3556SA/XSA
Pipelined Outputs
IDT71V3558SA/XSA
Features
◆ _{128K x 36, 256K x 18 memory configurations}
◆ _{Supports high performance system speed - 200 MHz (x18)}
(3.2 ns Clock-to-Data Access)
◆ _{Supports high performance system speed - 166 MHz (x36)}
(3.5 ns Clock-to-Data Access)
◆ _ZBTTM _{Feature - No dead cycles between write and read}
cycles
◆ _{Internally synchronized output buffer enable eliminates the}
need to control OE
◆ _{Single R/W (READ/WRITE) control pin}
◆ _{Positive clock-edge triggered address, data, and control}
signal registers for fully pipelined applications
◆ _{4-word burst capability (interleaved or linear)}
◆ _{Individual byte write (BW1 - BW4) control (May tie active)}
◆ _{Three chip enables for simple depth expansion}
◆ _{3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)}
◆ _{Optional- Boundary Scan JTAG Interface (IEEE 1149.1}
compliant)
◆ _{Packaged in a JEDEC standard 100-pin plastic thin quad}
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Description
The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT^TM, or
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be
it read or write.
The IDT71V3556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be
used to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three are
not asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
Pin Description Summary
A0-A17
CE1, CE2, CE2
OE
R/W
CEN
BW1, BW2, BW3, BW4
CLK
ADV/LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O0-I/O31, I/OP1-I/OP4
VDD, VDDQ
VSS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance b urst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
1
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
Synchronous
Static
Static
5281 tbl 01
OCTOBER 2010
DSC-5281/11