71V3558S200PFG Datasheet, PDF (10/28 Pages) Integrated Device Technology – 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address⁽¹⁾
1
1
1
0
0
1
0
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
5281 tbl 10
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
A1
A0
A1
A0
First Address
0
0
0
1
Second Address
0
1
1
0
Third Address
1
0
1
1
Fourth Address⁽¹⁾
1
1
0
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 3
A1
A0
1
0
1
1
0
0
0
1
Sequence 4
A1
A0
1
1
0
0
0
1
1
0
5281 tbl 11
Functional Timing Diagram ⁽¹⁾
CYCLE
n+29
n+30
n+31
CLOCK
ADDRESS⁽²⁾
(A0 - A16)
A29
A30
A31
CONTROL⁽²⁾
(R/W, ADV/LD, BWx)
C29
C30
C31
n+32
A32
C32
n+33
A33
C33
n+34
A34
C34
n+35
A35
C35
n+36
A36
C36
n+37
A37
C37
DATA⁽²⁾
I/O [0:31], I/O P[1:4]
D/Q27
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
,
5281 drw 03
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay
from the rising edge of clock.
6.1402