71V3558S200PFG Datasheet, PDF (8/28 Pages) Integrated Device Technology – 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 128K x 36, 165 fBGA
1
2
3
A
NC⁽²⁾
A7
CE1
B
NC
A6
CE2
C
I/OP3
NC
VDDQ
D
I/O17
I/O16
VDDQ
E
I/O19
I/O18
VDDQ
F
I/O21
I/O20
VDDQ
G
I/O23
I/O22
VDDQ
H
VDD⁽¹⁾
VDD⁽¹⁾
NC
J
I/O25
I/O24
VDDQ
K
I/O27
I/O26
VDDQ
L
I/O29
I/O28
VDDQ
M
I/O31
I/O30
VDDQ
N
I/OP4
NC
VDDQ
P
NC
NC⁽²⁾
A5
R
LBO
NC⁽²⁾
A4
4
5
6
BW3
BW2
CE2
BW4
BW1
CLK
VSS
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VSS
NC/T RST^{(3, 4)}
NC
A2
NC/TDI⁽³⁾
A1
A3
NC/TMS⁽³⁾
A0
7
8
CEN ADV/LD
R/W
OE
VSS
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD⁽¹⁾
VSS
NC/TDO⁽³⁾
A10
NC/TCK⁽³⁾
A11
9
NC⁽²⁾
NC⁽²⁾
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A13
A12
10
A8
A9
NC
I/O15
I/O13
I/O11
I/O9
NC
I/O7
I/O5
I/O3
I/O1
NC
A14
A15
11
NC
NC⁽²⁾
I/OP2
I/O14
I/O12
I/O10
I/O8
NC/ZZ⁽⁵⁾
I/O6
I/O4
I/O2
I/O0
I/OP1
NC
A16
5281 tbl 25
Pin Configuration - 256K x 18, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC⁽²⁾
A7
CE1
BW2
NC
CE2
CEN
ADV/LD
NC⁽²⁾
A8
A10
B
NC
A6
CE2
NC
BW1
CLK
R/W
OE
NC⁽²⁾
A9
NC⁽²⁾
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP1
D
NC
I/O8
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O7
E
NC
I/O9
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O6
F
NC
I/O10
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O5
G
NC
I/O11
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O4
H
VDD⁽¹⁾
VDD⁽¹⁾
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
NC/ZZ⁽⁵⁾
J
I/O12
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
NC
K
I/O13
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O2
NC
L
I/O14
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
NC
M
I/O15
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O0
NC
N
I/OP2
NC
VDDQ
VSS
NC/T RST^{(3, 4)}
NC
VDD⁽¹⁾
VSS
VDDQ
NC
NC
P
NC
NC⁽²⁾
A5
A2
NC/TDI⁽³⁾
A1
NC/TDO⁽³⁾
A11
A14
A15
NC
R
LBO
NC⁽²⁾
A4
A3
NC/TMS⁽³⁾
A0
NC/TCK⁽³⁾
A12
A13
A16
A17
NOTES:
5281 tbl 25a
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin H11 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
6.842