ICSSSTUAF32866C Datasheet, PDF (8/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Logic Diagram (1:1)
COMMERCIAL TEMPERATURE GRADE
G2
RESET
CLK ^H1
J1
CLK
D2 - D3,
D5 - D6,
22
D8 - D25
A3, T3
VREF
C1 ^G5
PAR_IN ^G1
LPS0
(Internal Node)
D ^CCEE
CLK
R
Q
D2 - D3,
22 ^{D5 - D6,}
D8 - D25
Parity
Check
0
DQ
1
CLK
R
D2 - D3,
D5 - D6,
22 ^{D8 - D25}
DQ
CLK
R
CE
1
D ^Q0
CLK
R
22 ^{Q2 - Q3,}
Q5 - Q6,
Q8 - Q25
A2 _PPO
D2 _QERR
G6
C0
CLK
2-Bit
Counter
R
LPS1
(Internal Node)
0
D
Q
1
CLK
R
Parity Logic Diagram for 1:1 Register Configuration (Positive Logic); C0 = 0, C1 = 0
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
8
ICSSSTUAF32866C
7100/9