ICSSSTUAF32866C Datasheet, PDF (22/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Register Timing
RESET
(1)
DCS
COMMERCIAL TEMPERATURE GRADE
tINACT
(1)
CSR
CLK ⁽¹⁾
(1)
CLK
(1)
D1 - D14
Q1 - Q14
(1)
PARIN
PPO
tRPHL
RESET to Q
tRPHL
RESET to PPO
QERR
(not used)
H, L, or X
tRPLH
RESET to QERR
H or L
Timing Diagram for the First SSTUAF32866C (1:2 Register-A Configuration) Device Used in a Pair; C0 = 1, C1 = 1; RESET
Switches from H to L
NOTE:
1.After RESET is switched from HIGH to LOW, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time
of tINACTMAX.
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
22
ICSSSTUAF32866C
7100/9