ICSSSTUAF32866C Datasheet, PDF (7/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Parity and Standby Function Table
RESET DCS CSR
Inputs¹
CLK CLK
Σ of Inputs = H
(D1 - D25)
PAR_IN²
Outputs
PPO
QERR³
H
L
X
↑
↓
Even
L
L
H
H
L
X
↑
↓
Odd
L
H
L
H
L
X
↑
↓
Even
H
H
L
H
L
X
↑
↓
Odd
H
L
H
H
X
L
↑
↓
Even
L
L
H
H
X
L
↑
↓
Odd
L
H
L
H
X
L
↑
↓
Even
H
H
L
H
X
L
↑
↓
Odd
H
L
H
H
H
H
↑
↓
X
X
PPO₀
H
X
X
L or H L or H
X
X
PPO₀
L
X or
X or
X or
X or
X or Floating X or Floating
L
Floating Floating Floating Floating
QERR₀
QERR₀
H
1 H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW to HIGH
↓ = HIGH to LOW
Data Inputs = D2, D3, D5, D6, D8 - D25 when C0 = 0 and C1 = 0.
Data Inputs = D2, D3, D5, D6, D8 - D14 when C0 = 0 and C1 = 1.
Data Inputs = D1 - D6, D8 - D10, D12, D13 when C0 = 1 and C1 = 1.
2 PAR_IN arrives one clock cycle after the data to which it applies when C0 = 0, and two clock cycles when
C0 = 1.
3 This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
7
ICSSSTUAF32866C
7100/9