ICSSSTUAF32866C Datasheet, PDF (19/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Register Timing
RESET
(1)
DCS
tINACT
COMMERCIAL TEMPERATURE GRADE
(1)
CSR
CLK ⁽¹⁾
(1)
CLK
(1)
D1 - D25
Q1 - Q25
(1)
PARIN
PPO
tRPHL
RESET to Q
tRPHL
RESET to PPO
QERR
H, L, or X
tRPLH
RESET to QERR
H or L
Timing Diagram for SSTUAF32866C Used as a Single Device; C0 = 0, C1 = 0, RESET Switches from H to L
NOTE:
1.After RESET is switched from HIGH to LOW, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time
of tINACTMAX.
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
19
ICSSSTUAF32866C
7100/9