ICSSSTUAF32866C Datasheet, PDF (28/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
COMMERCIAL TEMPERATURE GRADE
DUT
Out
CL = 5 pF
Test Point
RL = 1KΩ
Load Circuit: Partial-Parity-Out Load Circuit
CLK
CLK
VICR
tPLH
Output
VTT
VICR
VI(P-P)
tPHL
VTT
VOH
VOL
Load Circuit: Partial-Parity-Out Voltage Waveforms Propagation Delay Times (with respect to clock inputs)
LVCMOS
RESET
Input
Output
VDD/2
tRPHL
VTT
VIH
VIL
VOH
VOL
Load Circuit: Partial-Parity-Out Voltage Waveforms Propagation Delay Times (with respect to RESET input)
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
28
ICSSSTUAF32866C
7100/9