ICSSSTUAF32866C Datasheet, PDF (27/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
DUT
Out
VDD
RL = 50Ω
Test Point
CL = 10 pF
Load Circuit: High-to-Low Slew-Rate Adjustment
Output
VOH
80%
20%
dv_f
VOL
dt_f
Voltage Waveforms: High-to-Low Slew-Rate Adjustment
DUT
Out
VDD
RL = 1KΩ
Test Point
CL = 10 pF
Load Circuit: Error Output Measurements
LVCMOS
VCC
RESET
VCC/2
Input
0V
tPLH
VOH
Output
Waveform 2
0.15V
0V
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to RESET input)
DUT
Out
CL = 10 pF
Test Point
RL = 50Ω
Load Circuit: Low-to-High Slew-Rate Adjustment
Timing
Inputs
Output
Waveform 1
VICR
tHL
VICR
VCC/2
VI(PP)
VCC
VOL
Voltage Waveforms: Open Drain Output High-to-Low
Transition Time (with respect to clock inputs)
dt_r
dv_r
VOH
80%
20%
Output
VOL
Voltage Waveforms: Low-to-High Slew-Rate Adjustment
Timing
Inputs
Output
Waveform 2
VICR
tHL
VICR
0.15V
VI(PP)
VOH
0V
Voltage Waveforms: Open Drain Output Low-to-High
Transition Time (with respect to clock inputs)
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, Zo = 50Ω, input
slew rate = 1 V/ns ±20% (unless otherwise specified).
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
27
ICSSSTUAF32866C
7100/9