ICSSSTUAF32866C Datasheet, PDF (24/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Register Timing
COMMERCIAL TEMPERATURE GRADE
Timing Diagram for the Second SSTUAF32866C (1:2 Register-B Configuration) Device Used in a Pair; C0 = 1, C1 = 1, RESET Held
HIGH
NOTES:
1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse.
If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low.
2.PAR_IN is driven from PPO of the first SSTUAF32866 device.
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
24
ICSSSTUAF32866C
7100/9