ICSSSTUAF32866C Datasheet, PDF (15/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
VDD = 1.8V ± 0.1V
Symbol Parameter
Min.
Max. Units
fCLOCK Clock Frequency
410
MHz
tW
tACT1
tINACT2
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
1
ns
10
ns
15
ns
DCS before CLK↑, CLK↓, CSR HIGH; CSR before
CLK↑, CLK↓, DCS HIGH
0.7
tSU
Setup _{DCS before CLK↑, CLK↓, CSR LOW}
Time
0.5
ns
DODT, DOCKE, and data before CLK↑, CLK↓
0.5
PAR_IN before CLK↑, CLK↓
0.5
tH
Hold ^{DCS, DODT, DCKE, and data after CLK↑, CLK↓}
0.5
Time _{PAR_IN after CLK↑, CLK↓}
0.5
ns
1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
minimum time of tACT(max) after RESET is taken HIGH.
2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
time of tINACT(max) after RESET is taken LOW.
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
Symbol
fMAX
tPDM
tPDMSS
tPD
tLH
tHL
tPHL
tPLH
Parameter
Max Input Clock Frequency
Propagation Delay, single bit switching, CLK↑ to CLK↓ to Qn
Propagation Delay, simultaneous switching, CLK↑ to CLK↓ to Qn
Propagation Delay, CLK and CLK to PPO
LOW to HIGH Propagation Delay, CLK↑ to CLK↓ to QERR
HIGH to LOW Propagation Delay, CLK↑ to CLK↓ to QERR
HIGH to LOW Propagation Delay, RESET↓ to PPO to Qn↓
LOW to HIGH Propagation Delay, RESET↓ to QERR↑
VDD = 1.8V ± 0.1V
Min.
Max.
410
1.3
1.9
2
0.5
1.7
1.2
3
1
2.4
3
3
Units
MHz
ns
ns
ns
ns
ns
ns
ns
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
15
ICSSSTUAF32866C
7100/9