ICSSSTUAF32866C Datasheet, PDF (21/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Register Timing
COMMERCIAL TEMPERATURE GRADE
Timing Diagram for the First SSTUAF32866C (1:2 Register-A Configuration) Device Used in a Pair; C0 = 0, C1 = 1, RESET Held
HIGH
NOTE:
1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse.
If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low.
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
21
ICSSSTUAF32866C
7100/9