ICSSSTUAF32866C Datasheet, PDF (26/31 Pages) Integrated Device Technology – 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

ICSSSTUAF32866C
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Test Circuits and Waveforms (VDD = 1.8V ± 0.1V)
COMMERCIAL TEMPERATURE GRADE
CLK Inputs
TL = 50Ω
Test Point
RL = 100Ω
Test Point
DUT
CLK
CLK ^Out
TL = 350ps, 50Ω
CL = 30 pF
Simulation Load Circuit
VDD
RL = 1KΩ
Test Point
RL = 1KΩ
LVCMOS
RESET
Input
IDD
VDD/2
tINACT
10%
VDD/2
VDD
0V
tACT
90%
Voltage and Current Waveforms Inputs Active and Inactive
Times
Input
tW
VICR
VICR
VID
Voltage Waveforms - Pulse Duration
CLK
CLK
Input
tSU
VREF
VICR
tH
VID
VIH
VREF
VIL
Voltage Waveforms - Setup and Hold Times
CLK Inputs
ZO = 50Ω
ZO = 50Ω
Test
Point
Test
Point
DUT
CLK
Out
Test
Point
CLK
ZO = 50Ω
VDD/2
RL = 50Ω
Production-Test Load Circuit
CLK
CLK
Output
tPLH
VICR
VTT
VICR
VID
tPHL
VTT
VOH
VOL
Voltage Waveforms - Propagation Delay Times
LVCMOS
RESET
Input
Output
VDD/2
tRPHL
VTT
VIH
VIL
VOH
VOL
Voltage Waveforms - Propagation Delay Times
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and
Io = 0mA
3. All input pulses are supplied by generators having the following
characteristics: PRR ≤10MHz, Zo = 50Ω, input slew rate = 1 V/ns
±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per
measurement.
5. VTT = VREF = VDD/2
6. VIH = VREF + 250mV (AC voltage levels) for differential inputs.
VIH = VDD for LVCMOS input.
7. VIL = VREF - 250mV (AC voltage levels) for differential inputs.
VIL = GND for LVCMOS input.
8. VID = 600mV.
9. tPLH and tPHL are the same as tPDM.
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
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ICSSSTUAF32866C
7100/9