ICS1894-32 Datasheet, PDF (50/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Auto-Negotiation Fast Link Pulse Timing
The table below lists the significant time periods for the ICS1894-32 Auto-Negotiation Fast Link Pulse. The time
periods consist of timings of signals on the following pins:
• TP_TXP
• TP_TXN
The Auto-Negotiation Fast Link Pulse Timing Diagram shows the timing diagram for one pair of these differential
signals, for example TP_TXP minus TP_TXN.
Time
Period
Parameter
t1 Clock/Data Pulse Width
t2 Clock Pulse-to-Data Pulse Timing
t3 Clock Pulse-to-Clock Pulse Timing
t4 Fast Link Pulse Burst Width
t5 Fast Link Pulse Burst to Fast Link Pulse Burst
t6 Number of Clock/Data Pulses in a Burst
Conditions
–
–
–
–
–
–
Min.
–
55
110
–
10
15
Typ.
90
60
125
5
15
20
Max.
–
70
140
–
25
30
Units
ns
µs
µs
ms
ms
pulses
Auto-Negotiation Fast Link Pulse Timing Diagram
Differential
Twisted Pair
Transmit Signal
Clock
Pulse
t1
t2
Data
Pulse
t1
t3
Clock
Pulse
Differential
Twisted Pair
Transmit Signal
FLP Burst
t4
t5
FLP Burst
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 50
ICS1894-32 REV F 110209