ICS1894-32 Datasheet, PDF (35/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
100M MII: Synchronous Transmit Timing
The table below lists the significant time periods for the 100M MII Interface synchronous transmit timing. The time
periods consist of timings of signals on the following pins:
• TXCLK
• TXD[3:0]
• TXEN
• TXER
The 100M MII/100M Stream Interface Synchronous Transmit Timing Diagram figure shows the timing diagram for
the time periods.
Time
Period
Parameter
Conditions
t1 TXD[3:0], TXEN, TXER Setup to TXCLK Rise
–
t2 TXD[3:0], TXEN, TXER Hold after TXCLK Rise
–
Min.
15
0
Typ.
–
–
Max. Units
–
ns
–
ns
100M MII/100M Stream Interface Synchronous Transmit Timing Diagram
TXCLK
TXD[3:0]
TXEN
TXER
t1
t2
10M MII: Synchronous Transmit Timing
The table below lists the significant time periods for the 10M MII synchronous transmit timing. The time periods
consist of timings of signals on the following pins:
• TXCLK
• TXD[3:0]
• TXEN
• TXER
The 10M MII Synchronous Transmit Timing Diagram figure shows the timing diagram for the time periods.
Time
Period
Parameter
Conditions
t1 TXD[3:0], TXEN, TXER Setup to TXCLK Rise
–
t2 TXD[3:0], TXEN, TXER Hold after TXCLK Rise
–
Min.
375
0
Typ.
–
–
Max. Units
–
ns
–
ns
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 35
ICS1894-32 REV F 110209